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Single-Phase, Synchronous MOSFET Drivers
? V IN ( MAX ) ? ? ? ? η TOTAL ?
PD ( N L RESISTIVE ) = ? 1 ? ? ? ? ? ? R DS ( ON )
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied due to the squared term in the
switching-loss equation above. If the high-side MOSFET
chosen for adequate R DS(ON) at low battery voltages
becomes extraordinarily hot when biased from V IN(MAX) ,
consider choosing another MOSFET with lower parasitic
capacitance.
For the low-side MOSFET (N L ), the worst-case power
dissipation always occurs at the maximum input voltage:
? ? V OUT ? ? ? I LOAD ? 2
? ?
The worst case for MOSFET power dissipation occurs
under heavy load conditions that are greater than
I LOAD(MAX) , but are not quite high enough to exceed the
current limit and cause the fault latch to trip. The
MOSFETs must have a good-sized heatsink to handle the
overload power dissipation. The heat sink can be a large
copper field on the PCB or an externally mounted device.
An optional Schottky diode only conducts during the
dead time when both the high-side and low-side
MOSFETs are off. Choose a Schottky diode with a
forward voltage low enough to prevent the low-side
MOSFET body diode from turning on during the dead
time, and a peak current rating higher than the peak
inductor current. The Schottky diode must be rated to
handle the average power dissipation per switching
cycle. This diode is optional and can be removed if effi-
ciency is not critical.
IC Power Dissipation and
Thermal Considerations
Power dissipation in the IC package comes mainly from
driving the MOSFETs. Therefore, it is a function of both
switching frequency and the total gate charge of the
selected MOSFETs. The total power dissipation when
both drivers are switching is given by:
PD ( IC ) = I BIAS × 5 V
where I BIAS is the bias current of the 5V supply calcu-
lated in the 5V Bias Supply (V DD ) section. The rise in
die temperature due to self-heating is given by the
following formula:
? T J = Θ JA × PD ( IC )
where PD(IC) is the power dissipated by the device,
and Θ JA is the package’s thermal resistance. The typi-
cal thermal resistance is 42°C/W for the 3mm x 3mm
TQFN package.
Avoiding dV/dt Turning on the
Low-Side MOSFET
At high input voltages, fast turn-on of the high-side
MOSFET can momentarily turn on the low-side MOSFET
due to the high dV/dt appearing at the drain of the low-
side MOSFET. The high dV/dt causes a current flow
through the Miller capacitance (C RSS ) and the input
capacitance (C ISS ) of the low-side MOSFET. Improper
selection of the low-side MOSFET that results in a high
ratio of C RSS /C ISS makes the problem more severe. To
avoid this problem, minimize the ratio of C RSS /C ISS
when selecting the low-side MOSFET. Adding a 1 ? to
4.7 ? resistor between BST and C BST can slow the
high-side MOSFET turn-on. Similarly, adding a small
capacitor from the gate to the source of the high-side
MOSFET has the same effect. However, both methods
work at the expense of increased switching losses.
Layout Guidelines
The MAX8791/MAX8791B MOSFET driver sources and
sinks large currents to drive MOSFETs at high switch-
ing speeds. The high di/dt can cause unacceptable
ringing if the trace lengths and impedances are not well
controlled. The following PCB layout guidelines are rec-
ommended when designing with the MAX8791/
MAX8791B:
1) Place all decoupling capacitors as close as possi-
ble to their respective IC pins.
2) Minimize the length of the high-current loop from
the input capacitor, the upper switching MOSFET,
and the low-side MOSFET back to the input-capacitor
negative terminal.
3) Provide enough copper area at and around the
switching MOSFETs and inductors to aid in thermal
dissipation.
4) Connect GND of the MAX8791/MAX8791B as close
as possible to the source of the low-side MOSFETs.
A sample layout is available in the MAX8786 evaluation kit.
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